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19-3064; Rev 1; 12/04
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
General Description
The MAX5522-MAX5525 are dual, 10-bit, ultra-lowpower, voltage-output, digital-to-analog converters (DACs) offering rail-to-rail buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and consume less than 5A, making the devices suitable for lowpower and low-voltage applications. A shutdown mode reduces overall current, including the reference input current, to just 0.18A. The MAX5522-MAX5525 use a 3-wire serial interface that is compatible with SPITM, QSPITM, and MICROWIRETM. Upon power-up, the MAX5522-MAX5525 outputs are driven to zero scale, providing additional safety for applications that drive valves or for other transducers that need to be off during power-up. The zero-scale outputs enable glitch-free power-up. The MAX5522 accepts an external reference input and provides unity-gain outputs. The MAX5523 contains a precision internal reference and provides a buffered external reference output with unity-gain DAC outputs. The MAX5524 accepts an external reference input and provides force-sense outputs. The MAX5525 contains a precision internal reference and provides a buffered external reference output with force-sense DAC outputs. The MAX5524/MAX5525 are available in a 4mm x 4mm x 0.8mm, 12-pin, thin QFN package. The MAX5522/ MAX5523 are available in an 8-pin MAX package. All devices are guaranteed over the extended -40C to +85C temperature range. For 12-bit compatible devices, refer to the MAX5532- MAX5535 data sheet. For 8-bit compatible devices, refer to the MAX5512-MAX5515 data sheet. Ultra-Low 5A Supply Current Shutdown Mode Reduces Supply Current to 0.18A (max) Single +1.8V to +5.5V Supply Small 4mm x 4mm x 0.8mm Thin QFN Package Internal Reference Sources 8mA of Current (MAX5523/MAX5525) Flexible Force-Sense-Configured Rail-to-Rail Output Buffers Fast 16MHz, 3-Wire, SPI-/QSPI-/MICROWIRECompatible Serial Interface TTL- and CMOS-Compatible Digital Inputs with Hysteresis Glitch-Free Outputs During Power-Up
Features
MAX5522-MAX5525
Ordering Information
PART MAX5522EUA MAX5523EUA MAX5524ETC MAX5525ETC TEMP RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C PIN-PACKAGE 8 MAX 8 MAX 12 Thin QFN-EP* 12 Thin QFN-EP*
*EP = Exposed paddle (internally connected to GND).
Selector Guide
PART MAX5522EUA MAX5523EUA MAX5524ETC MAX5525ETC OUTPUTS Unity gain Unity gain Force sense Force sense REFERENCE External Internal External Internal TOP MARK -- -- AACK AACL
Applications
Portable Battery-Powered Devices Instrumentation Automatic Trimming and Calibration in Factory or Field Programmable Voltage and Current Sources Industrial Process Control and Remote Industrial Devices Remote Data Conversion and Monitoring Chemical Sensor Cell Bias for Gas Monitors Programmable LCD Bias
SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corp.
Pin Configurations
TOP VIEW
CS 1 SCLK 2 DIN 3 REFIN(MAX5522) 4 REFOUT(MAX5523) 8 OUTA
MAX5522 MAX5523
7 GND 6 VDD 5 OUTB
MAX Pin Configurations continued at end of data sheet. 1
________________________________________________________________ Maxim Integrated Products
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
ABSOLUTE MAXIMUM RATINGS
VDD to GND ..............................................................-0.3V to +6V OUTA, OUTB to GND .................................-0.3V to (VDD + 0.3V) FBA, FBB to GND .......................................-0.3V to (VDD + 0.3V) SCLK, DIN, CS to GND ..............................-0.3V to (VDD + 0.3V) REFIN, REFOUT to GND ............................-0.3V to (VDD + 0.3V) Continuous Power Dissipation (TA = +70C) 12-Pin Thin QFN (derate 16.9mW/C above +70C).....1349mW 8-Pin MAX (derate 5.9mW/C above +70C) .............471mW Operating Temperature Range ...........................-40C to +85C Storage Temperature Range .............................-65C to +150C Junction Temperature ......................................................+150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Resolution Integral Nonlinearity (Note 1) SYMBOL N INL VDD = 5V, VREF = 4.096V VDD = 1.8V, VREF = 1.024V Guaranteed monotonic, VDD = 5V, VREF = 4.096V Guaranteed monotonic, VDD = 1.8V, VREF = 1.024V Offset Error (Note 2) Offset-Error Temperature Drift Gain Error (Note 3) Gain-Error Temperature Coefficient Power-Supply Rejection Ratio Resolution Integral Nonlinearity (Note 1) PSRR N INL VDD = 5V, VREF = 3.9V VDD = 1.8V, VREF = 1.2V Guaranteed monotonic, VDD = 5V, VREF = 3.9V Guaranteed monotonic, VDD = 1.8V, VREF = 1.2V VDD = 5V, VREF = 3.9V VDD = 1.8V, VREF = 1.2V VDD = 5V, VREF = 3.9V VDD = 1.8V, VREF = 1.2V 1.8V VDD 5.5V 10 1 1 0.2 0.2 1 1 2 GE 0.5 0.5 4 2 2 4 4 1 LSB 1 20 20 mV V/C LSB ppm/C STATIC ACCURACY (MAX5523/MAX5525 INTERNAL REFERENCE) Bits LSB GE VDD = 5V, VREF = 4.096V VDD = 1.8V, VREF = 1.024V VOS VDD = 5V, VREF = 4.096V VDD = 1.8V, VREF = 1.024V CONDITIONS MIN 10 1 1 0.2 0.2 1 1 2 0.5 0.5 4 85 2 2 4 4 1 LSB 1 20 20 mV V/C LSB ppm/C dB TYP MAX UNITS Bits LSB
STATIC ACCURACY (MAX5522/MAX5524 EXTERNAL REFERENCE)
Differential Nonlinearity (Note 1)
DNL
Differential Nonlinearity (Note 1)
DNL
Offset Error (Note 2) Offset-Error Temperature Drift Gain Error (Note 3) Gain-Error Temperature Coefficient
VOS
2
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Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Power-Supply Rejection Ratio Reference-Input Voltage Range Reference-Input Impedance SYMBOL PSRR VREFIN RREFIN Normal operation In shutdown No external load, VDD = 1.8V Initial Accuracy VREFOUT No external load, VDD = 2.5V No external load, VDD = 3V No external load, VDD = 5V Output-Voltage Temperature Coefficient Line Regulation VTEMPCO TA = -40C to +85C (Note 4) VREFOUT < VDD - 200mV (Note 5) 0 IREFOUT 1mA, sourcing, VDD = 1.8V, VREF = 1.2V Load Regulation 0 IREFOUT 8mA, sourcing, VDD = 5V, VREF = 3.9V -150A IREFOUT 0, sinking 0.1Hz to 10Hz, VREF = 3.9V Output Noise Voltage 10Hz to 10kHz, VREF = 3.9V 0.1Hz to 10Hz, VREF = 1.2V 10Hz to 10kHz, VREF = 1.2V Short-Circuit Current (Note 6) Capacitive Load Stability Range Thermal Hysteresis Reference Power-Up Time (from Shutdown) Long-Term Stability DAC OUTPUTS (OUTA, OUTB) Capacitive Driving Capability VDD = 5V VDD = 1.8V (Note 7) (Note 8) REFOUT unloaded, VDD = 5V REFOUT unloaded, VDD = 1.8V 1.197 1.913 2.391 3.828 CONDITIONS 1.8V VDD 5.5V 0 4.1 2.5 1.214 1.940 2.425 3.885 12 2 0.3 0.3 0.2 150 600 50 450 30 14 0 to 10 200 5.4 4.4 200 mA nF ppm ms ppm/ 1khrs pF 65 65 mA 14 14 VP-P 1.231 1.967 2.459 3.941 30 200 2 2 V/A ppm/C V/V V MIN TYP 85 VDD MAX UNITS dB V M G
MAX5522-MAX5525
REFERENCE INPUT (MAX5522/MAX5524)
REFERENCE OUTPUT (MAX5523/MAX5525)
CL VDD = 5V, VOUT set to full scale, OUT shorted to GND, source current VDD = 5V VOUT set to 0V, OUT shorted to VDD, sink current VDD = 1.8V, VOUT set to full scale OUT shorted to GND, source current VDD = 1.8V, VOUT set to 0V, OUT shorted to VDD, sink current
1000
Short-Circuit Current (Note 6)
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3
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
ELECTRICAL CHARACTERISTICS (continued)
(VDD = +1.8V to +5.5V, OUT_ unloaded, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER SYMBOL CONDITIONS Coming out of shutdown (MAX5522/MAX5524) DAC Power-Up Time Coming out of standby (MAX5523/MAX5525) Output Power-Up Glitch FB_ Input Current DIGITAL INPUTS (SCLK, DIN, CS) 4.5V VDD 5.5V Input High Voltage VIH 2.7V < VDD 3.6V 1.8V VDD 2.7V 4.5V VDD 5.5V Input Low Voltage Input Leakage Current Input Capacitance DYNAMIC PERFORMANCE Voltage-Output Slew Rate Voltage-Output Settling Time SR Positive and negative (Note 10) 0.1 to 0.9 of full scale to within 0.5 LSB (Note 10) 0.1Hz to 10Hz Output Noise Voltage 10Hz to 10kHz POWER REQUIREMENTS Supply Voltage Range VDD VDD = 5V MAX5523/MAX5525 Supply Current (Note 9) IDD MAX5522/MAX5524 VDD = 3V VDD = 1.8V VDD = 5V VDD = 3V VDD = 1.8V Standby Supply Current Shutdown Supply Current IDDSD IDDPD MAX5523/MAX5525 (Note 9) (Note 9) VDD = 5V VDD = 3V VDD = 1.8V 1.8 7.0 6.4 7.0 3.8 3.8 4.7 3.3 2.8 2.4 0.05 5.5 8.0 8.0 8.0 5.0 5.0 6.0 4.5 4.0 3.5 0.25 A A A V VDD = 5V VDD = 1.8V VDD = 5V VDD = 1.8V 10 660 80 55 620 476 VP-P V/ms s VIL IIN CIN 2.7V < VDD 3.6V 1.8V VDD 2.7V (Note 9) 0.05 10 2.4 2.0 0.7 x VDD 0.8 0.6 0.3 x VDD 0.5 A pF V V CL = 100pF VDD = 5V VDD = 1.8V VDD = 1.8V to 5.5V MIN TYP 3 3.8 0.4 10 10 mV pA s MAX UNITS
4
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Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
TIMING CHARACTERISTICS
(VDD = +4.5V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Serial Clock Frequency DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Pulse-Width High SCLK Pulse-Width Low CS Pulse-Width High SCLK Rise to CS Rise Hold Time CS Fall to SCLK Rise Setup Time SCLK Fall to CS Fall Setup CS Rise to SCK Rise Hold Time SYMBOL fSCLK tDS tDH tCH tCL tCSW tCSH tCSS tCSO tCS1 CONDITIONS MIN 0 15 0 24 24 100 0 20 0 20 TYP MAX 16.7 UNITS MHz ns ns ns ns ns ns ns ns ns
MAX5522-MAX5525
TIMING CHARACTERISTICS (VDD = 4.5V to 5.5V )
TIMING CHARACTERISTICS
(VDD = +1.8V to +5.5V, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25C.)
PARAMETER Serial Clock Frequency DIN to SCLK Rise Setup Time DIN to SCLK Rise Hold Time SCLK Pulse-Width High SCLK Pulse-Width Low CS Pulse-Width High SCLK Rise to CS Rise Hold Time CS Fall to SCLK Rise Setup Time SCLK Fall to CS Fall Setup CS Rise to SCK Rise Hold Time SYMBOL fSCLK tDS tDH tCH tCL tCSW tCSH tCSS tCSO tCS1 CONDITIONS MIN 0 24 0 40 40 150 0 30 0 30 TYP MAX 10 UNITS MHz ns ns ns ns ns ns ns ns ns
TIMING CHARACTERISTICS (VDD = 1.8V to 5.5V )
Note 1: Linearity is tested within codes 24 to 1020. Note 2: Offset is tested at code 24. Note 3: Gain is tested at code 1023. For the MAX5524/MAX5525, FB_ is connected to its respective OUT_. Note 4: Guaranteed by design. Not production testsed Note 5: VDD must be a minimum of 1.8V. Note 6: Outputs can be shorted to VDD or GND indefinitely, provided that package power dissipation is not exceeded. Note 7: Optimal noise performance is at 2nF load capacitance. Note 8: Thermal hysteresis is defined as the change in the initial +25C output voltage after cycling the device from TMAX to TMIN. Note 9: All digital inputs at VDD or GND. Note 10: Load = 10k in parallel with 100pF, VDD = 5V, VREF = 4.096V (MAX5522/MAX5524) or VREF = 3.9V (MAX5523/MAX5525).
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5
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
Typical Operating Characteristics
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5522/MAX5524)
MAX5522 toc01
SUPPLY CURRENT vs. TEMPERATURE (MAX5522/MAX5524)
MAX5522 toc02
SUPPLY CURRENT vs. SUPPLY VOLTAGE (MAX5523/MAX5525)
9 8 SUPPLY CURRENT (A) 7 6 5 4 3 2 1 0
MAX5522 toc03
5.0 4.5 4.0 SUPPLY CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
5.0 4.5 4.0 SUPPLY CURRENT (A) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
10
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V)
-40
-15
10
35
60
85
1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V)
TEMPERATURE (C)
SUPPLY CURRENT vs. TEMPERATURE (MAX5523/MAX5525)
MAX5522 toc04
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5522/MAX5524)
MAX5522 toc05
SHUTDOWN SUPPLY CURRENT vs. TEMPERATURE (MAX5523/MAX5525)
MAX5522 toc06
10 9 8 SUPPLY CURRENT (A) 7 6 5 4 3 2 1 0 -40 -15 10 35 60
1000 SHUTDOWN SUPPLY CURRENT (nA)
1000 SHUTDOWN SUPPLY CURRENT (nA)
100
100
10
10
1
1
0.1 85 -40 -15 10 35 60 85 TEMPERATURE (C) TEMPERATURE (C)
0.1 -40 -15 10 35 60 85 TEMPERATURE (C)
STANDBY SUPPLY CURRENT vs. TEMPERATURE (MAX5523/MAX5525)
MAX5522 toc07
SUPPLY CURRENT vs. CLOCK FREQUENCY
MAX5522 toc08
SUPPLY CURRENT vs. LOGIC INPUT VOLTAGE
4.5 4.0 SUPPLY CURRENT (mA) 3.5 3.0 2.5 2.0 1.5 1.0 0.5 VDD = 5V ALL DIGITAL INPUTS SHORTED TOGETHER
MAX5522 toc09
5.0 4.5 STANDBY SUPPLY CURRENT (A) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 -40 -15 10 35 60 VREF = 1.9V VREF = 1.2V VREF = 3.9V VREF = 2.4V
1000 CS = LOGIC LOW CODE = 0 SUPPLY CURRENT (A) VDD = 5V 100
5.0
10
VDD = 1.8V
1 85 0.01 0.1 1 10 100 1000 10000 100000 TEMPERATURE (C) FREQUENCY (kHz)
0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 LOGIC INPUT VOLTAGE (V)
6
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Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25C, unless otherwise noted.)
MAX5522-MAX5525
INL vs. INPUT CODE (VDD = VREF = 1.8V)
MAX5522 toc10
INL vs. INPUT CODE (VDD = VREF = 5V)
MAX5522 toc11
DNL vs. INPUT CODE (VDD = VREF = 1.8V)
0.05 0.04 0.03 DNL (LSB) 0.02 0.01 0 -0.01 -0.02 -0.03
MAX5522 toc12
0.4 0.2 0 INL (LSB)
0.4 0.2 0 INL (LSB) -0.2 -0.4 -0.6 -0.8 -1.0 -1.2
0.06
-0.2 -0.4 -0.6 -0.8 -1.0 -1.2 0 200 400 600 800 1000 1200 DIGITAL INPUT CODE
0
200
400
600
800
1000
1200
0
200
400
600
800
1000
1200
DIGITAL INPUT CODE
DIGITAL INPUT CODE
DNL vs. INPUT CODE (VDD = VREF = 5V)
MAX5522 toc13
OFFSET VOLTAGE vs. TEMPERATURE
MAX5522 toc14
GAIN ERROR CHANGE vs. TEMPERATURE
0.08 GAIN ERROR CHANGE (LSB) 0.06 0.04 0.02 0 -0.02 -0.04 -0.06 -0.08 VDD = 5V VREF = 3.9V
MAX5522 toc15
0.04 0.03 0.02 DNL (LSB) 0.01 0 -0.01 -0.02 -0.03 0 200 400 600 800 1000
1.0 0.8 0.6 OFFSET VOLTAGE (mV) 0.4 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
VDD = 5V VREF = 3.9V
0.10
1200
-40
-15
10
35
60
85
-0.10 -40 -15 10 35 60 85 TEMPERATURE (C)
DIGITAL INPUT CODE
TEMPERATURE (C)
DIGITAL FEEDTHROUGH RESPONSE
MAX5522 toc16
DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT
MAX5522 toc17
DAC OUTPUT LOAD REGULATION vs. OUTPUT CURRENT
1.9435 DAC OUTPUT VOLTAGE (V) 1.9430 1.9425 1.9420 1.9415 1.9410 1.9405 VDD = 5.0V DAC CODE = MIDSCALE VREF = 3.9V
MAX5522 toc18
0.6050 CS 5V/div SCLK 5V/div DIN 5V/div OUT 50mV/div VDD = 1.8V DAC CODE = MIDSCALE VREF = 1.2V
1.9440
ZERO SCALE DAC OUTPUT VOLTAGE (V) 0.6048
0.6046
0.6044
0.6042
20s/div
0.6040 -1000-800 -600 -400 -200 0 200 400 600 800 1000 DAC OUTPUT CURRENT (A)
1.9400 -10 -8 -6 -4 -2 0 2 4 6 8 10 DAC OUTPUT CURRENT (mA)
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7
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25C, unless otherwise noted.)
DAC OUTPUT VOLTAGE vs. OUTPUT SOURCE CURRENT
MAX5522 toc19
DAC OUTPUT VOLTAGE vs. OUTPUT SINK CURRENT
4.5 DAC OUTPUT VOLTAGE (V) 4.0 3.5 3.0 2.5 2.0 1.5 1.0 VDD = 3V VDD = 5V VREF = VDD
CODE = MIDSCALE
MAX5522 toc20
OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 1.8V, VREF = 1.2V)
MAX5522 toc21
5 VREF = VDD CODE = MIDSCALE 4 OUTPUT VOLTAGE (V)
5.0
3
VDD = 5V
VOUT 200mV/div
2
VDD = 3V
1 VDD = 1.8V 0 0.001
0.5 1 10 100 0 0.001 0.01 0.1
VDD = 1.8V 1 10 100 100s/div
0.010
0.100
OUTPUT SOURCE CURRENT (mA)
OUTPUT SINK CURRENT (mA)
OUTPUT LARGE-SIGNAL STEP RESPONSE (VDD = 5V, VREF = 3.9V)
MAX5522 toc22
OUTPUT MINIMUM SERIES RESISTANCE vs. LOAD CAPACITANCE
FOR NO OVERSHOOT MINIMUM SERIES RESISTANCE () 500 400 300 200 100 0 0.0001 0.001 VOUT 500mV/div
MAX5522 toc23
POWER-UP OUTPUT VOLTAGE GLITCH
MAX5522 toc24
600
VDD 2V/div
VOUT 10mV/div
200s/div
0.01
0.1
1
10
100
20ms/div
CAPACITANCE (F)
MAJOR CARRY OUTPUT VOLTAGE GLITCH (CODE 7FFh TO 800h) (VDD = 5V, VREF = 3.9V)
MAX5522 toc25
REFERENCE OUTPUT VOLTAGE vs. TEMPERATURE
MAX5522 toc26
REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT
VDD = 1.8V REFERENCE OUTPUT VOLTAGE (V) 1.219 1.218 1.217 1.216 1.215 1.214
MAX5522 toc27
3.940 REFERENCE OUTPUT VOLTAGE (V) 3.935 3.930 3.925 3.920 3.915 3.910 3.905 3.900
VDD = 5V
1.220
VOUT AC-COUPLED 5mV/div
100s/div
-40
-15
10
35
60
85
-500
1500
3500
5500
7500
TEMPERATURE (C)
REFERENCE OUTPUT CURRENT (A)
8
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Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25C, unless otherwise noted.)
REFERENCE OUTPUT VOLTAGE vs. REFERENCE OUTPUT CURRENT
MAX5522 toc28
MAX5522-MAX5525
REFERENCE OUTPUT VOLTAGE vs. SUPPLY VOLTAGE
1.21748 1.21746 1.21744 1.21742 1.21740 1.21738 1.21736 1.21734 1.21732
MAX5522 toc29
REFERENCE LINE-TRANSIENT RESPONSE (VREF = 1.2V)
MAX5522 toc30
3.92 VDD = 5V REFERENCE OUTPUT VOLTAGE (V) 3.91
1.21750 REFERENCE OUTPUT VOLTAGE (mV)
2.8V VDD 1.8V VREF 500mV/div
3.90
3.89
3.88 -500 2000 4500 7000 9500 12,000 14,500 REFERENCE OUTPUT CURRENT (A)
1.21730 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 6.0 SUPPLY VOLTAGE (V) 100s/div
REFERENCE LINE-TRANSIENT RESPONSE (VREF = 3.9V)
MAX5522 toc31
REFERENCE LOAD TRANSIENT (VDD = 1.8V)
MAX5522 toc32
5.5V VDD 4.5V VREF 500mV/div 3.9V REFOUT SOURCE CURRENT 0.5mA/div VREF 500mV/div
100s/div
200s/div
REFERENCE LOAD TRANSIENT (VDD = 5V)
MAX5522 toc33
REFERENCE LOAD TRANSIENT (VDD = 1.8V)
MAX5522 toc34
REFOUT SOURCE CURRENT 0.5mA/div
REFOUT SINK CURRENT 50A/div
VREF 500mV/div 3.9V
VREF 500mV/div
200s/div
200s/div
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9
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
Typical Operating Characteristics (continued)
(VDD = 5.0V, VREF = 4.096V (MAX5522/MAX5524), VREF = 3.9V (MAX5523/MAX54525), TA = +25C, unless otherwise noted.)
REFERENCE LOAD TRANSIENT (VDD = 5V)
MAX5522 toc35
REFERENCE PSRR vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO (dB) VDD = 1.8V 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 1000
MAX5522 toc36
80 REFOUT SINK CURRENT 100A/div
VREF 500mV/div 3.9V
200s/div
FREQUENCY (kHz)
REFERENCE PSRR vs. FREQUENCY
POWER-SUPPLY REJECTION RATIO (dB) VDD = 5V 70 60 50 40 30 20 10 0 0.01 0.1 1 10 100 1000
MAX5522 toc37
REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 1.8V, VREF = 1.2V)
MAX5522 toc38
80
100V/div
1s/div
FREQUENCY (kHz)
REFERENCE OUTPUT NOISE (0.1Hz TO 10Hz) (VDD = 5V, VREF = 3.9V)
MAX5522 toc39
DAC-TO-DAC CROSSTALK
MAX5522 toc40
OUTA 1V/div
100V/div OUTB AC-COUPLED 10mV/div
OUTB AT FULL SCALE 1s/div 400s/div
10
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Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
Pin Description
PIN MAX5522 1 2 3 4 -- -- -- 5 6 7 8 -- -- MAX5523 1 2 3 -- 4 -- -- 5 6 7 8 -- -- MAX5524 1 2 3 4 -- 5, 11 6 7 8 9 10 12 EP MAX5525 1 2 3 -- 4 5, 11 6 7 8 9 10 12 EP NAME CS SCLK DIN REFIN REFOUT N.C. FBB OUTB VDD GND OUTA FBA Exposed Paddle FUNCTION Active-Low Digital Chip-Select Input Serial-Interface Clock Input Serial-Interface Data Input Reference Input Reference Output No Connection. Leave N.C. inputs unconnected (floating) or connected to GND. Channel B Feedback Input Channel B Analog Voltage Output Power Input. Connect VDD to a 1.8V to 5.5V power supply. Bypass VDD to GND with a 0.1F capacitor. Ground Channel A Analog Voltage Output Channel A Feedback Input Exposed Paddle. Connect EP to GND.
MAX5522-MAX5525
Functional Diagrams
VDD
REFIN
POWERDOWN CONTROL
MAX5522
INPUT REGISTER DAC REGISTER
10-BIT DAC OUTA
SCLK DIN CS
CONTROL LOGIC AND SHIFT REGISTER INPUT REGISTER DAC REGISTER 10-BIT DAC
OUTB
GND
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11
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
Functional Diagrams (continued)
VDD
POWERDOWN CONTROL
2-BIT PROGRAMMABLE REFERENCE INPUT REGISTER DAC REGISTER
REF BUF
REFOUT
MAX5523
10-BIT DAC OUTA CONTROL LOGIC AND SHIFT REGISTER INPUT REGISTER DAC REGISTER 10-BIT DAC OUTB
SCLK DIN CS
GND
VDD
REFIN
POWERDOWN CONTROL
MAX5524
INPUT REGISTER DAC REGISTER
10-BIT DAC OUTA
SCLK DIN CS
CONTROL LOGIC AND SHIFT REGISTER INPUT REGISTER DAC REGISTER 10-BIT DAC
FBA
OUTB
FBB GND
12
______________________________________________________________________________________
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
Functional Diagrams (continued)
VDD
MAX5522-MAX5525
POWERDOWN CONTROL
2-BIT PROGRAMMABLE REFERENCE INPUT REGISTER DAC REGISTER
REF BUF
REFOUT
MAX5525
10-BIT DAC OUTA CONTROL LOGIC AND SHIFT REGISTER INPUT REGISTER DAC REGISTER 10-BIT DAC OUTB
SCLK DIN CS
FBA
FBB GND
Detailed Description
The MAX5522-MAX5525 dual, 10-bit, ultra-low-power, voltage-output DACs offer rail-to-rail buffered voltage outputs. The DACs operate from a 1.8V to 5.5V supply and require only 5A (max) supply current. These devices feature a shutdown mode that reduces overall current, including the reference input current, to just 0.18A (max) The MAX5523/MAX5525 include an internal reference that saves additional board space and can source up to 8mA, making it functional as a system reference. The 16MHz, 3-wire serial interface is compatible with SPI, QSPI, and MICROWIRE protocols. When VDD is applied, all DAC outputs are driven to zero scale with virtually no output glitch. The MAX5522/ MAX5523 output buffers are configured in unity gain and come in MAX packages. The MAX5524/MAX5525 output buffers are configured in force sense allowing users to externally set voltage gains on the output (an output-amplifier inverting input is available). The MAX5524/MAX5525 come in 4mm x 4mm thin QFN packages.
Digital Interface
The MAX5522-MAX5525 use a 3-wire serial interface that is compatible with SPI/QSPI/MICROWIRE protocols (Figures 1 and 2). The MAX5522-MAX5525 include a single, 16-bit, input shift register. Data loads into the shift register through the serial interface. CS must remain low until all 16 bits are clocked in. The 16 bits consist of 4 control bits (C3-C0), 10 data bits (D9-D0) (Table 1), and 2 sub-bits (S1 and S0). D9-D0 are the DAC data bits and S1 and S0 are the sub-bits. The sub-bits must be set to zero for proper operation. Following the control bits, data loads MSB first, D9-D0. The control bits C3-C0 control the MAX5522-MAX5525, as outlined in Table 2. Each DAC channel includes two registers: an input register and a DAC register. The input register holds input data. The DAC register contains the data updated to the DAC output. The double-buffered register configuration allows any of the following: * Loading the input registers without updating the DAC registers * Updating the DAC registers from the input registers * Updating all the input and DAC registers simultaneously
______________________________________________________________________________________
13
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
Table 1. Serial Write Data Format
CONTROL MSB C3 C2 C1 C0 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 S1 DATA BITS LSB S0
Sub-bits S1 to S0 must be set to zero for proper operation.
tCH SCLK tDS DIN tCS0 tCSS CS tCSW tCS1 C3 tDH C2 tCL
C1
S0 tCSH
Figure 1. Timing Diagram
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
DIN
C3
C2
C1
C0
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
S1
S0
CONTROL BITS CS
DATA BITS
SUB-BITS COMMAND EXECUTED
Figure 2. Register Loading Diagram
14
______________________________________________________________________________________
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
Table 2. Serial-Interface Programming Commands
CONTROL BITS C3 0 0 0 0 0 0 0 0 C2 0 0 0 0 1 1 1 1 C1 0 0 1 1 0 0 1 1 C0 0 1 0 1 0 1 0 1 INPUT DATA D9-D0 XXXXXXXXXX 10-bit data 10-bit data -- -- -- -- -- SUB-BITS S1 AND S0 00 00 00 -- -- -- -- -- FUNCTION No operation; command is ignored. Load input register A from shift register; DAC registers unchanged; DAC outputs unchanged. Load input register B from shift register; DAC registers unchanged; DAC outputs unchanged. Command reserved. Do not use. Command reserved. Do not use. Command reserved. Do not use. Command reserved. Do not use. Command reserved. Do not use. Load DAC registers A and B from respective input registers; DAC outputs A and B updated; MAX5523/MAX5525 enter normal operation if in standby or shutdown; MAX5522/MAX5524 enter normal operation if in shutdown. Load input register A and DAC register A from shift register; DAC output A updated; Load DAC register B from input register B; DAC output B updated; MAX5523/MAX5525 enter normal operation if in standby or shutdown; MAX5522/MAX5524 enter normal operation if in shutdown. Load input register B and DAC register B from shift register; DAC output B updated; Load DAC register A from input register A; DAC output A updated; MAX5523/MAX5525 enter normal operation if in standby or shutdown; MAX5522/MAX5524 enter normal operation if in shutdown. Command reserved. Do not use. MAX5523/MAX5525 enter standby*, MAX5522/MAX5524 enter shutdown. For the MAX5523/MAX5525, D9 and D8 configure the internal reference voltage (Table 3). MAX5522-MAX5525 enter normal operation; DAC outputs reflect existing contents of DAC registers. For the MAX5523/MAX5525, D9 and D8 configure the internal reference voltage (Table 3). MAX5522-MAX5525 enter shutdown; DAC outputs set to high impedance. For the MAX5523/MAX5525, D9 and D8 configure the internal reference voltage (Table 3). Load input registers A and B and DAC registers A and B from shift register; DAC outputs A and B updated; MAX5523/MAX5525 enter normal operation if in standby or shutdown; MAX5522/MAX5524 enter normal operation if in shutdown.
MAX5522-MAX5525
1
0
0
0
10-bit data
00
1
0
0
1
10-bit data
00
1
0
1
0
10-bit data
00
1 1
0 1
1 0
1 0
-- D9, D8, XXXXXXXX
-- 00
1
1
0
1
D9, D8, XXXXXXXX
00
1
1
1
0
D9, D8, XXXXXXXX
00
1
1
1
1
10-bit data
00
X = Don't care. *Standby mode can be entered from normal operation only. It is not possible to enter standby mode from shutdown. ______________________________________________________________________________________ 15
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
Power Modes
The MAX5522-MAX5525 feature two power modes to conserve power during idle periods. In normal operation, the device is fully operational. In shutdown mode, the device is completely powered down, including the internal voltage reference in the MAX5523/MAX5525. The MAX5523/MAX5525 also offer a standby mode in which all circuitry is powered down except the internal voltage reference. Standby mode keeps the reference powered up while the remaining circuitry is shut down, allowing it to be used as a system reference. It also helps reduce the wake-up delay by not requiring the reference to power up when returning to normal operation. Shutdown Mode The MAX5522-MAX5525 feature a software-programmable shutdown mode that reduces the supply current and the interface input-current to 0.18A (max). Writing an input control word with control bits C[3:0] = 1110 (Table 2) places the device in shutdown mode. In shutdown, the MAX5522/MAX5524 reference input and DAC output buffers go high impedance. Placing the MAX5523/ MAX5525 into shutdown turns off the internal reference and the DAC output buffers go high impedance. The serial interface still remains active for all devices. Table 2 shows several commands that bring the MAX5522-MAX5525 back to normal operation. The power-up time from shutdown is required before the DAC outputs are valid. Note: For the MAX5523/MAX5525, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation first before entering standby mode. Standby Mode (MAX5523/MAX5525 Only) The MAX5523/MAX5525 feature a software-programmable standby mode that reduces the typical supply current to 3A (max). Standby mode powers down all circuitry except the internal voltage reference. Place the device in standby mode by writing an input control word with control bits C[3:0] = 1100 (Table 2). The internal reference and serial interface remain active while the DAC output buffers go high impedance. For the MAX5523/MAX5525, standby mode cannot be entered directly from shutdown mode. The device must be brought into normal operation first before entering standby mode. To enter standby from shutdown, issue the command to return to normal operation followed immediately by the command to go into standby. Table 2 shows several commands that bring the MAX5523/MAX5525 back to normal operation. When transitioning from standby mode to normal operation, only the DAC power-up time is required before the DAC outputs are valid.
Reference Input
The MAX5522/MAX5524 accept a reference with a voltage range extending from 0 to VDD. The output voltage (VOUT) is represented by a digitally programmable voltage source as: VOUT = (VREF x N / 256) x gain where N is the numeric value of the DAC's binary input code (0 to 1023), VREF is the reference voltage, gain is the externally set voltage gain for the MAX5524, and gain is one for the MAX5522. In shutdown mode, the reference input enters a highimpedance state with an input impedance of 2.5G (typ).
Reference Output
The MAX5523/MAX5525 internal voltage reference is software configurable to one of four voltages. Upon power-up, the default reference voltage is 1.214V. Configure the reference voltage using D8 and D9 data bits (Table 3) when the control bits are as follows C[3:0] = 1100, 1101, or 1110 (Table 2). VDD must be kept at a minimum of 200mV above VREF for proper operation.
Table 3. Reference Output Voltage Programming
D9 0 0 1 1 D8 0 1 0 1 REFERENCE VOLTAGE (V) 1.214 1.940 2.425 3.885
16
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Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
Applications Information
1-Cell and 2-Cell Circuits
See Figure 3 for an illustration of how to power the MAX5522-MAX5525 with either one lithium-ion battery or two alkaline batteries. The low current consumption of the devices make the MAX5522-MAX5525 ideal for battery-powered applications.
Programmable Current Source
See the circuit in Figure 4 for an illustration of how to configure the MAX5524/MAX5525 as a programmable current source for driving an LED. The MAX5524/ MAX5525 drive a standard NPN transistor to program the current source. The current source (ILED) is defined in the equation in Figure 4.
MAX5522-MAX5525
VDD 1.8V VALKALINE 3.3V 2.2V VLITHIUM 3.3V 536k +1.25V 0.1F REFIN DAC VOUT VOUT (1.22mV / LSB)
MAX6006
(1A, 1.25V SHUNT REFERENCE)
0.01F
MAX5524
GND
V x NDAC VOUT = REFIN 1024 NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
Figure 3. Portable Application Using Two Alkaline Cells or One Lithium Coin Cell
V+ LED ILED REFIN DAC VOUT 2N3904 REFIN DAC VOUT VOUT VOUT = VBIAS + (IT x R)
1/2 MAX5524
FB TRANSDUCER VBIAS IT R
1/2 MAX5524
V x NDAC ILED = REFIN 1024 x R NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
FB
R
V x NDAC VBIAS = REFIN 1024 NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE.
Figure 4. Programmable Current Source Driving an LED
Figure 5. Transimpedance Configuration for a Voltage-Biased Current-Output Transducer 17
______________________________________________________________________________________
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
Voltage Biasing a Current-Output Transducer
See the circuit in Figure 5 for an illustration of how to configure the MAX5524/MAX5525 to bias a current-output transducer. In Figure 5, the output voltage of the MAX5524/MAX5525 is a function of the voltage drop across the transducer added to the voltage drop across the feedback resistor R. An example of a custom fixed gain using the MAX5524/ MAX5525 force-sense output is shown in Figure 8. In this example, R1 and R2 set the gain for VOUTA. VOUTA = [(VREFIN x NA) / 1024] x [1 + (R2 / R1)] where NA represents the numeric value of the DAC input code.
Unipolar Output
Figure 6 shows the MAX5524 in a unipolar output configuration with unity gain. Table 4 lists the unipolar output codes.
Self-Biased Two-Electrode Potentiostat Application
See the circuit in Figure 10 for an illustration of how to use the MAX5525 to bias a two-electrode potentiostat on the input of an ADC.
Bipolar Output
The MAX5524 output can be configured for bipolar operation as shown in Figure 7. The output voltage is given by the following equation: VOUT_ = VREFIN x [(NA - 512) / 512] where NA represents the decimal value of the DAC's binary input code. Table 5 shows the digital codes (offset binary) and the corresponding output voltage for the circuit in Figure 7.
Power Supply and Bypassing Considerations
Bypass the power supply with a 4.7F capacitor in parallel with a 0.1F capacitor to GND. Minimize lengths to reduce lead inductance. If noise becomes an issue, use shielding and/or ferrite beads to increase isolation. For the thin QFN package, connect the exposed pad to ground.
Configurable Output Gain
The MAX5524/MAX5525 have force-sense outputs, which provide a connection directly to the inverting terminal of the output op amp, yielding the most flexibility. The advantage of the force-sense output is that specific gains can be set externally for a given application. The gain error for the MAX5524/MAX5525 is specified in a unity-gain configuration (op-amp output and inverting terminals connected), and additional gain error results from external resistor tolerances. Another advantage of the force-sense DAC is that it allows many useful circuits to be created with only a few simple external components.
Table 4. Unipolar Code Table (Gain = +1)
DAC CONTENTS MSB 1111 1000 1000 0111 0000 0000 1111 0000 0000 1111 0000 0000 LSB 1100 0100 0000 1100 0100 0000 ANALOG OUTPUT +VREF (1023/1024) +VREF (513/1024) +VREF (512/1024) = +VREF/2 +VREF (511/1024) +VREF (1/1024) 0V
Table 5. Bipolar Code Table (Gain = +1)
REFIN DAC OUT_
DAC CONTENTS MSB 1111 1111 0000 0000 1111 0000 0000 LSB 1100 0100 0000 1100 0100 0000
ANALOG OUTPUT +VREF (511/512) +VREF (1/512) 0V -VREF (1/512) -VREF (511/512) -VREF (512/512) = -VREF
MAX5524
FB_ V x NA VOUT = REFIN 1024 NA IS THE DAC INPUT CODE (0 TO 1023 DECIMAL).
1000 1000 0111 0000 0000
Figure 6. Unipolar Output Circuit
18
______________________________________________________________________________________
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
Layout Considerations
Digital and AC transient signals coupling to GND can create noise at the output. Use proper grounding techniques, such as a multilayer board with a low-inductance ground plane. Wire-wrapped boards and sockets are not recommended. For optimum system performance, use printed circuit (PC) boards. Good PC board ground layout minimizes crosstalk between DAC outputs, reference inputs, and digital inputs. Reduce crosstalk by keeping analog lines away from digital lines.
V 255 - NPOT x NDAC VOUT = REFIN 1+ 1024 255
MAX5522-MAX5525
(
)
NDAC IS THE NUMERIC VALUE OF THE DAC INPUT CODE. NPOT IS THE NUMERIC VALUE OF THE POT INPUT CODE. 1.8V VDD 5.5V REFIN
DAC
VOUT VOUT H
CS1
1/2 MAX5524
FB SCLK DIN W
MAX5401 SOT-POT 100k
5PPM/C RATIOMETRIC TEMPCO L
10k
10k
CS2
V+ VOUT DAC REFIN OUT_ V-
Figure 9. Software-Configurable Output Gain
1/2 MAX5524
FB_ REF OUT IF FB RF TO ADC WE SENSOR
VOUTA R2 FBA VOUT1 V R2 x NDACA VOUT1 = REFIN 1+ 1024 R1
DAC
TO ADC
Figure 7. Bipolar Output Circuit
1/2 MAX5525
REFIN DAC
CE
(
)
BAND GAP REFOUT CL TO ADC
NDACA IS THE NUMERIC VALUE OF THE DAC A INPUT CODE.
1/2 MAX5524
DAC
R1
VOUTB
VOUT2 VOUT2 = VREFIN x NDACB 1024
Figure 10. Self-Biased Two-Electrode Potentiostat Application
FBB
NDACB IS THE NUMERIC VALUE OF THE DAC B INPUT CODE.
Figure 8. Separate Force-Sense Outputs Create Unity and Greater-than-Unity DAC Gains Using the Same Reference ______________________________________________________________________________________ 19
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
Pin Configurations (continued)
REF DAC OUTA IF FBA CS SCLK DIN 1 2 3 RF
TOP VIEW
TO ADC FBA 12 N.C. 11 OUTA 10
WE
9
GND VDD OUTB
MAX5525
SENSOR REF DAC OUTB CE
MAX5524 MAX5525
8 7
4 FBB BAND GAP REFOUT CL REFIN(MAX5524) REFOUT(MAX5525)
5 N.C.
6 FBB
TO ADC
THIN QFN
Figure 11. Driven Two-Electrode Potentiostat Application
Chip Information
TRANSISTOR COUNT: 10,688 PROCESS: BiCMOS
20
______________________________________________________________________________________
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX5522-MAX5525
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
1 2
______________________________________________________________________________________
24L QFN THIN.EPS
21
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs MAX5522-MAX5525
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE 12, 16, 20, 24L THIN QFN, 4x4x0.8mm
21-0139
C
2 2
22
______________________________________________________________________________________
Dual, Ultra-Low-Power, 10-Bit, Voltage-Output DACs
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
8LUMAXD.EPS
MAX5522-MAX5525
4X S
8
8
INCHES DIM A A1 A2 b MIN 0.002 0.030 MAX 0.043 0.006 0.037
MILLIMETERS MAX MIN 0.05 0.75 1.10 0.15 0.95
y 0.500.1
E
H
0.60.1
c D e E H L
1
1
0.60.1
S
D
BOTTOM VIEW
0.014 0.010 0.007 0.005 0.120 0.116 0.0256 BSC 0.120 0.116 0.198 0.188 0.026 0.016 6 0 0.0207 BSC
0.25 0.36 0.13 0.18 2.95 3.05 0.65 BSC 2.95 3.05 5.03 4.78 0.41 0.66 0 6 0.5250 BSC
TOP VIEW
A2
A1
A
c e b L
SIDE VIEW
FRONT VIEW
PROPRIETARY INFORMATION TITLE:
PACKAGE OUTLINE, 8L uMAX/uSOP
APPROVAL DOCUMENT CONTROL NO. REV.
21-0036
1 1
J
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 23 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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